Simulation of Low Power Architecture of Finite State Machine

With the predominance of mobile devices, rising energy costs, and an awareness of green practices,power consumption has become a major concern for design engineers. When power consumption is analyzed, it breaks down into two main components: static or leakage power, which occurs naturally when components are idle and powered on; and dynamic power, which is the power consumed when components are switching. While both static and dynamic power remain important targets for power reduction, this paper will focus on architectural level techniques for reducing power. To further improve efficiency, designers must use innovative techniques at the architectural level. Further, analysis shows that datapath circuits often consume large amounts of dynamic power due to their large circuit size and high switching activities. They are especially impactful because they are often a major portion of the circuits that must be powered on for an extended time. In this paper, we address the issue of low power realization of FSMs using decomposition and a gated clock architecture [9]. We decompose an state machine into two interacting machines and develop it at architectural level .To lower the power consumption of these circuits,designer propose a architecture level method to compute power in finite state machine .